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High-Level Synthesis of Digital Circuits
Jendrušák, Ján ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with practical test of high-level synthesis as a digital circuits design method and its current progress in creating RTL models. At first main tasks of HLS will be described together with C++ library of classes called SystemC, which implements hardware constructs, notion of time and hardware datatypes with arbitrary bit width. After that thesis focuses on discrete Fourier transform and its fast form of computation – fast Fourier transform. In the practical part of thesis reference FFT model is written in C++ language, which is later edited appropriately a synthesized with Stratus High-Level Synthesis tool into several hardware architectures.
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Automatic signal evaluation using Fourier transform
Rudžík, Matej ; Zuth, Daniel (referee) ; Huzlík, Rostislav (advisor)
This master’s thesis deals with signal evaluation using Fourier transform. In the theoretical section, different methods of signal analysis with an emphasis on a Fast Fourier Transform are described. Theoretical section also contains description of common machinery faults and their diagnosis using frequency spectrum analysis. In the practical section, an algorithm for signal evaluation with an emphasis on coherence condition was designed in the Matlab environment. This algorithm was later used to evaluate submitted signals.
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Automatic signal evaluation using Fourier transform
Rudžík, Matej ; Zuth, Daniel (referee) ; Huzlík, Rostislav (advisor)
This master’s thesis deals with signal evaluation using Fourier transform. In the theoretical section, different methods of signal analysis with an emphasis on a Fast Fourier Transform are described. Theoretical section also contains description of common machinery faults and their diagnosis using frequency spectrum analysis. In the practical section, an algorithm for signal evaluation with an emphasis on coherence condition was designed in the Matlab environment. This algorithm was later used to evaluate submitted signals.
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High-Level Synthesis of Digital Circuits
Jendrušák, Ján ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with practical test of high-level synthesis as a digital circuits design method and its current progress in creating RTL models. At first main tasks of HLS will be described together with C++ library of classes called SystemC, which implements hardware constructs, notion of time and hardware datatypes with arbitrary bit width. After that thesis focuses on discrete Fourier transform and its fast form of computation – fast Fourier transform. In the practical part of thesis reference FFT model is written in C++ language, which is later edited appropriately a synthesized with Stratus High-Level Synthesis tool into several hardware architectures.
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